(1). Field of the Invention
The present invention relates to a field effect transistor (FET) which is formed in a silicon layer located on an insulating film, or a silicon on insulator (SOI) substrate. The SOI substrate has an insulating film and a thin silicon layer formed over a conductive substrate used as the conventional substrate to form the FET. The present invention also relates to a method of manufacturing such a field effect transistor.
(2). Description of the Related Art
Recently, a field effect transistor is formed on an SOI substrate (SOI-FET) in stead of a conventional bulk semiconductor substrate. The SOI-FET is formed in a thin silicon film (SOI layer) formed on an insulating film. As a junction capacitance is reduced, the SOI-FET can operate with a high-speed. Particularly, a fully depleted SOI-FET formed in the SOI layer is known as a low-power device which has a small parasitic capacitance and a subthreshold swing smaller than that of the conventional bulk semiconductor substrate. The fully depleted transistor has a depletion layer, which expands to the bottom surfaces of a source region and a drain region, when a voltage is supplied to a gate electrode thereof. As an expansion of depletion layers of the fully depleted SOI-FET is defined by a thickness of the SOI layer, a short channel effect can be restrained. Thus, for achieving the fully depleted operation of the SOI-FET, it is necessary to reduce the thickness of the SOI layer, as a device becomes microscopic.
The low-power device is shown in The article magazine of Institute of Electronics, Information and Communication Engineers C-II Vol. J81-C-II No. 3, pp. 313–319, “Deep Sub-0.1 μm MOSFET's with Very Thin SOI Layer for Ultra-Low Power Applications”, published in March 1998 (hereinafter a first thesis). The shorter the gate length of the SOI-FET, the thinner the thickness of the SOI layer is. In the case where the gate length is 0.1 μm, the thickness of the SOI layer should be set 20 nm or below. Therefore, it is necessary to reduce the thickness of the SOI layer, if the SOI-FET becomes smaller. The thickness of the SOI layer becomes thinner, the deterioration of the drive current occurs since the enlargement of the parasitic resistance in the source and drain regions becomes remarkable. Nowadays, a silicide technology using titanium (Ti) or cobalt (Co) is adopted to restrain the deterioration of the drive current. A metallic silicide layer is comprised of refractory metal and silicon. Titanium disilicide (TiSi2) and Cobalt disilicide (CoSi2) are widely used for their low resistivity.
However, when the specific contact resistivity between a metallic silicide layer and a silicon layer exceeds 1×10−7 Ω-cm2, and the thickness of the SOI layer located under the metallic silicide layer is less than 10 nm, the parasitic resistance would be increased so as to increase a resistance of a diffusion layer. Asa result, the drive current of the SOI-FET might be reducing. This relationship is shown in IEEE ELECTRON DEVICE LETTERS, VOL. 15 No. 9, and pp. 363–365, “Optimization of Series Resistance in Sub-0.2 μm SOI MOSFET's”, published in September 1998 (hereinafter a second thesis).
Currently, no metallic materials which have a specific contact resistivity less than 1×10−7 Ω-cm2 have been known. Hence, it is required that the SOI-FET layer be comprised of a silicide layer and a non-silicide layer over 10 nm in a diffusion layer. However, when a gate length becomes smaller, the thickness of the SOI layer become too thin to form such silicide and silicon multi-layered structure.